ds1707/DS1708 3.3 and 5.0 volt micromonitor ds1707/DS1708 022698 1/10 features ? holds microprocessor in check during power tran- sients ? automatically restarts microprocessor after power failure ? monitors pushbutton for external override ? accurate 5%, 10% or 20% resets for 3.3 systems and 5% or 10% resets for 5.0 volt systems ? eliminates the need for discrete components ? 20% tolerance compatible with 3.0 volt systems ? pin compatible with the maxim max707/max708 in 8pin dip and 8pin soic packages ? 8pin dip, 8pin soic and 8pin m sop packages available ? industrial temperature range 40 c to +85 c pin assignment rst rst nc nmi 1 2 3 4 pbrst v cc gnd in 8 7 6 5 8 7 6 5 1 2 3 4 pbrst v cc gnd in rst rst nc nmi 8pin dip (300 mil) 8pin soic (150 mil) 1 2 3 4 8 7 6 5 pbrst v cc gnd in rst rst nc nmi 8pin m sop (118 mil) see mech. drawings section ds1707 and DS1708_/r/s/t pin description pbrst pushbutton reset input v cc power supply gnd ground in input nmi nonmaskable interrupt nc no connect rst active low reset output rst active high reset output description the ds1707/DS1708 3.3 or 5.0 volt micromonitor moni- tors three vital conditions for a microprocessor: power supply, voltage sense, and external override. a preci- sion temperaturecompensated reference and comparator circuit monitors the status of v cc at the device and at an upstream point for maximum protec- tion. when the sense input detects an outoftolerance condition a nonmaskable interrupt is generated. as the voltage at the device degrades an internal power fail signal is generated which forces the reset to an active state. when v cc returns to an intolerance condition, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize.
ds1707/DS1708 022698 2/10 the third function the ds1707/DS1708 performs is pushbutton reset control. the ds1707/DS1708 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. operation power monitor the ds1707/DS1708 detects outoftolerance power supply conditions and warns a processorbased sys- tem of impending power failure. when v cc falls below the minimum v cc tolerance, a comparator outputs the rst and rst signals. rst and rst are excellent con- trol signals for a microprocessor, as processing is stopped at the last possible moment of valid v cc . on powerup, rst and rst are kept active for a minimum of 130 ms to allow the power supply and processor to stabilize. pushbutton reset the ds1707/DS1708 provides an input pin for direct connection to a pushbutton reset (see figure 2). the pushbutton reset input requires an active low signal. internally, this input is debounced and timed such that rst and rst signals of at least 130 ms minimum will be generated. the 130 ms delay commences as the push- button reset input is released from the low level. the pushbutton can be initiated by connecting the nmi out- put to the pbrst input as shown in figure 3. nonmaskable interrupt the ds1707/DS1708 generates a nonmaskable inter- rupt (nmi ) for early warning of a power failure. a preci- sion comparator monitors the voltage level at the in pin relative to an onchip reference generated by an inter- nal band gap. the in pin is a high impedance input allowing for a userdefined sense point. an external resistor voltage divider network (figure 5) is used to interface with high voltage signals. this sense point may be derived from a regulated supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 1.25 volts, the proper val- ues for r1 and r2 can be determined by the equation as shown in figure 5. proper operation of the ds1707/DS1708 requires that the voltage at the in pin be limited to v cc . therefore, the maximum allowable voltage at the supply being monitored (v max ) can also be derived as shown in figure 5. a simple approach to solving the equation is to select a value for r2 high enough to keep power consumption low, and solve for r1. the flexibility of the in input pin allows for detection of power loss at the earliest point in a power supply sys- tem, maximizing the amount of time for system shut down between nmi and rst/rst . when the supply being monitored decays to the voltage sense point, the ds1707/DS1708 pulses the nmi out- put to the active state for a minimum 200 m s. the nmi power fail detection circuitry also has builtin hysteresis of 100 m v. the supply must be below the voltage sense point for approximately 5 m s before a low nmi will be generated. in this way, power supply noise is removed from the monitoring function, preventing false inter- rupts. during a powerup, any detected in pin levels below v tp by the comparator are disabled from gener- ating an interrupt until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . connecting nmi to pbrst would allow the nonmask- able interrupt to generate an automatic reset when an outoftolerance condition occurred in a monitored supply. an example is shown in figure 3.
ds1707/DS1708 022698 3/10 micromonitor block diagram figure 1 + + t.c. reference digital sampler digital sampler digital delay level sense and debounce in v cc pbrst nmi rst rst pushbutton reset figure 2 gnd in rst nc rst pbrst v cc DS1708 rst nmi 8051 m p 5v upstream supply voltage int0 pushbutton reset controlled by nmi figure 3 gnd in nc rst pbrst v cc ds1707 rst nmi m p rst upstream supply voltage 5v
ds1707/DS1708 022698 4/10 timing diagram: pushbutton reset figure 4 rst pbrst rst v ih t rst v il t pdly t pb v oh v ol nonmaskable interrupt circuit example figure 5 gnd in nc rst pbrst v cc DS1708 rst nmi to m p r1 r2 v sense v sense r1 r2 r2 x1.25 v max v sense v tp xv cc example: v sense = 4.70 volts at the trip point v cc = 3.3 volts 10k w = r2 therefore: 4.70 1.25 x3.3 12.4 volts maximum 4.5 r1 10k 10k x1.25 r1 27.6k
ds1707/DS1708 022698 5/10 timing diagram: nonmaskable interrupt figure 6 v in > 1.25v nmi v ol v oh v tp(max) v tp(max) v tp v tp v tp(min) v tp(min) t ipd t ipd timing diagram: power down figure 7 rst slews with v cc v ol v oh v cctp(min) v cctp(max) v cctp t rpd t f v cc rst rst
ds1707/DS1708 022698 6/10 timing diagram: power up figure 8 rst rst rst rst v oh v ol t rpu v cctp(max) v cctp v cctp(min) v cc t r
ds1707/DS1708 022698 7/10 absolute maximum ratings* voltage on v cc pin relative to ground 0.5v to +7.0v voltage on i/o relative to ground** 0.5v to v cc +0.5v operating temperature 40 c to +85 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. **the voltage input limits on in and pbrst can be exceeded if the input current is less than 10 ma. recommended dc operating conditions (40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc 1.0 5.5 v 1 pbrst input high level v ih 2.0 v cc 0.5 v cc +0.3 v 1, 3 1, 4 pbrst input low level v il 0.03 +0.5 v 1 dc electrical characteristics (40 c to +85 c; v cc =1.2v to 5.5v) parameter symbol min typ max units notes v cc trip point ds1707 v cctp 4.50 4.65 4.75 v 1 v cc trip point DS1708 v cctp 4.25 4.40 4.50 v 1 v cc trip point DS1708t v cctp 3.00 3.08 3.15 v 1 v cc trip point DS1708s v cctp 2.85 2.93 3.00 v 1 v cc trip point DS1708r v cctp 2.55 2.63 2.70 v 1 input leakage i il 1.0 +1.0 m a 2 output current @ 2.4 volts i oh 350 m a 3 output current @ 0.4 volts i ol 10 ma 3 output voltage v oh v cc 0.1 v 3 operating current @ v cc < 5.5 volts i cc 60 m a 5 operating current @ v cc < 3.6 volts i cc 50 m a 5 in input trip point v tp 1.20 1.25 1.30 v 1 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf
ds1707/DS1708 022698 8/10 ac electrical characteristics (40 c to +85 c; v cc =1.2v to 5.5v) parameter symbol min typ max units notes pbrst = v il t pb 150 ns reset active time t rst 130 205 285 ms v cc detect to rst and rst t rpd 5 8 m s 7 v cc slew rate t f 20 m s v cc detect to rst and rst t rpu 130 205 285 ms 6 v cc slew rate t r 0 ns pbrst stable low to rst and rst t pdly 250 ns vin detect to nmi t ipd 5 8 m s 7 notes: 1. all voltages are referenced to ground. 2. pbrst is internally pulled up to v cc with an internal impedance of 40k w typical. 3. v cc 2.4 volts 4. v cc < 2.4 volts 5. measured with outputs open and all inputs at v cc or ground. 6. t r = 5 m s 7. noise immunity pulses < 2 m s at v cctp minimum will not cause a reset.
ds1707/DS1708 022698 9/10 part marking codes 8pin m sop (118 mil) 1234 8765 abcd wwy a, b, c and d represents the device type and tolerance. abcd 707_ ds1707 708_ DS1708 708r DS1708r 708s DS1708s 708t DS1708t wwy represents the device manufacturing w ork w eek, and y ear.
ds1707/DS1708 022698 10/10 data sheet revision summary the following represent the key differences between 01/09/96 and 06/17/97 version of the ds1707/08 data sheet. please review this summary carefully. 1. page 7 add the following statement to the aabsolute maximum ratingso the voltage input limits on in and pbrst can be exceeded if the input current is less than 10 ma.
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